1. Field of the Invention
The present invention relates to a semiconductor device and a stacked semiconductor device in which a circuit board and a semiconductor chip are connected by leads.
2. Description of Related Art
In recent years, semiconductor devices of a ball grid array (BGA) type or a fine pitch ball grid array (FBGA) type have been used as a semiconductor device in which a semiconductor chip such as a dynamic random access memory (DRAM) is mounted. Also, Japanese Patent Laid-Open No. 2007-311643 and Japanese Patent Laid-Open No. 2006-013553 disclose semiconductor devices of a stacked FBGA (sFBGA) type in which a plurality of FBGA-type semiconductor devices are stacked.
In Japanese Patent Laid-Open No. 2007-311643, an sFBGA-type semiconductor device is described. A semiconductor chip is mounted on a wiring circuit board in the semiconductor device in each layer. Interlayer connection terminals connecting the wiring circuit boards in the layers are disposed in circuit board regions located outside the semiconductor chips.
In Japanese Patent Laid-Open Nos. 2006-013553, 10-144723 and 9-246331, a semiconductor device, in which leads that are provided on a carrier are connected to electrode pads formed on a semiconductor chip, is described. The semiconductor device described in Japanese Patent Laid-Open No. 2006-013553 has a semiconductor chip on which bonding pads are formed and a flexible wiring circuit board (carrier) on which wiring is formed. Leads are projecting from the wiring on the flexible wiring circuit board. The leads are connected to the bonding pads of the semiconductor chip.
The semiconductor chip and the flexible wiring circuit board are connected to each other by an elastomer. A solder resist is formed on the major surface of the flexible wiring circuit board. Solder bumps are connected to bump lands in the wiring on the flexible wiring circuit board. The leads projecting from the wiring circuit board pass through openings formed in the elastomer and the wiring circuit board. The leads are connected to the bonding pads of the semiconductor chip (see FIG. 10 in Japanese Patent Laid-Open No. 2006-013553).
Presently, there is a strong demand for reducing the thickness of semiconductor devices. The inventor of the present invention has found problems described below as a result of a study about the reduction in thickness of semiconductor devices.
In the semiconductor device described in Japanese Patent Laid-Open No. 2006-013553, connecting the leads to the semiconductor chip requires separating the leads and the semiconductor chip by a distance equal to or larger than a predetermined value before connecting (bonding) the leads. This distance is required for press-cutting of the leads with a bonding tool. If this distance is small, the leads can be not cut and connection failure results. Therefore, there is a problem that, if this distance is set larger than the predetermined value, the thickness of the elastomer provided between the semiconductor chip and the circuit board cannot be reduced.
Japanese Patent Laid-Open No. 2006-013553 discloses to reduce the thickness of the semiconductor device. The semiconductor device in Japanese Patent Laid-Open No. 2006-013553 is provided with an elastomer for relaxing stress concentration on the solder bumps due to the difference between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of a mount substrate. In a semiconductor device having solder balls provided at positions overlapping the chip mount region for the semiconductor chip in particular, a film of an elastomer having a thickness sufficient for stress relaxation is used. For the above-described reasons, it is difficult to reduce the thickness of the semiconductor device described in Japanese Patent Laid-Open No. 2006-013553. The semiconductor devices described in Japanese Patent Laid-Open Nos. 10-144723 and 9-246331 also have solder balls provided at positions overlapping the chip mount region for the semiconductor chip and therefore have the same problem regarding reducing the thickness of the semiconductor devices.